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April 11, 2025

Best Prototype Award Paper

A 3D NAND flash compatible compute-in-memory array featuring multi-bit weight storage, 128 NAND layers, a 40-bitline multiply-and-accumulate operation, a new program scheme for minimizing back pattern dependency, and an integrated signed weight bitline scheme was demonstrated in a standard 65 nanometer technology. Combining the proposed circuit techniques, our design achieves a cell current error less than 0.15μA and an inference accuracy within 1.3% (64 stack) and 2.8% (128 stack) of the ideal software results for the VGG-16 neural network architecture and CIFAR-10 dataset.

Source:

https://doi.org/10.36227/techrxiv.174439324.42202505/v1

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