The Time for Time‑Domain Computing Is Now

Executive Summary

The exponential growth of artificial intelligence (AI) and data‑intensive workloads has exposed fundamental inefficiencies in conventional von Neumann architectures. The separation of memory and compute leads to excessive data movement, resulting in the well‑known memory wall—a dominant limiter of performance, energy efficiency, and scalability. Compute-In-Memory (CiM) has emerged as a compelling alternative, demonstrating orders‑of‑magnitude improvements in energy efficiency by co‑locating compute with data.

Industry momentum now clearly signals that incremental improvements are no longer sufficient. Just two weeks ago, Unconventional AI announced a $475 million seed round, one of the largest in semiconductor and AI history, explicitly targeting the AI scaling and energy crunch with radically new, analog‑inspired hardware approaches. This announcement reflects a broad recognition that traditional digital accelerators are approaching fundamental limits in power, cost, and scalability.

Most CiM efforts to date rely on charge‑domain or current‑domain computation. While promising, these approaches face inherent challenges related to limited dynamic range, sensitivity to noise and parasitics, process variation, and increasing incompatibility with advanced CMOS nodes operating at ever‑lower supply voltages.

This white paper presents time‑domain computing as a fundamentally different and scalable paradigm for CiM. By encoding information in time rather than voltage or current amplitude, time‑domain architectures naturally support accumulation, enable ultra‑low‑power operation, and leverage highly scalable digital circuits for signal conversion. We argue that time‑domain CiM directly addresses the shortcomings highlighted by current analog approaches and aligns with the industry’s urgent push for new computing substrates.

Background: The Memory Wall and CiM Motivation

Modern AI workloads are dominated by linear algebra operations—matrix‑vector and matrix‑matrix multiplications—where data reuse is high and arithmetic intensity is modest. In conventional systems:

Energy per memory access far exceeds energy per arithmetic operation
Off‑chip and even on‑chip data movement dominates total power
Scaling compute units without addressing memory bandwidth yields diminishing returns

Compute-In-Memory (CiM) mitigates these issues by embedding computation within or adjacent to memory arrays, drastically reducing data movement. Experimental demonstrations have shown significant gains in TOPS/W for neural‑network workloads.

The urgency of this problem is now widely acknowledged at the industry level. The AI ecosystem is facing a scaling crunch driven by power density, cooling constraints, and unsustainable operating costs in data centers. The unprecedented $475 M seed investment into Unconventional AI underscores a shared conclusion: new physical computing paradigms are required, not just better digital accelerators.

However, the choice of computation domain inside memory critically determines scalability, manufacturability, and long‑term robustness.

Limitations of Charge‑ and Current‑Domain CiM

Most existing analog CiM architectures are typically implemented using either charge‑domain or current‑domain representations.

Charge‑Domain Approaches

Encode signals as voltages on capacitive elements
Dynamic range fundamentally limited by supply voltage
Increasingly fragile as supply voltages scale downwa

Current‑Domain Approaches

Use resistive or transconductance‑based summation along bitlines
Susceptible to IR drop, RC parasitics, and temperature gradients
Global summation nodes exacerbate noise and variability

The analog approaches raise legitimate concerns around scalability, calibration overhead, and long‑term reliability. The need for frequent calibration, compensation circuits, and high‑precision ADCs often erodes the theoretical energy advantages of CiM.

These challenges are not merely implementation artifacts—they are intrinsic to amplitude‑based computation in deeply scaled CMOS technologies.

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A New Paradigm: Time‑Domain Computation

Core Concept

Time‑domain computing encodes information in temporal quantities—such as pulse width, delay, or arrival time—rather than voltage or current magnitude.

Key insight:

When signals are represented in time, multiplication naturally maps to time modulation, and addition emerges implicitly through temporal accumulation.

This behavior resembles a domino effect: pulses generated by individual memory cells propagate and accumulate in time without requiring explicit analog summation networks.

Why Time Is Fundamentally Different

Time as a signal dimension offers properties that directly address CiM challenges:

Not bounded by supply voltage → enables wide dynamic range
Naturally compatible with digital logic → robust and scalable
Resilient to routing parasitics → delays add predictably

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Advantages of Time‑Domain CiM

Wide Dynamic Range

Unlike voltage or current, time encoding is not constrained by supply rails. This makes time‑domain CiM particularly attractive in advanced CMOS nodes where supply voltages continue to scale downward.

Subthreshold and Ultra‑Low‑Power Operation

Time‑domain circuits can operate effectively in subthreshold or near‑threshold regimes:

Reduced dynamic power
Exponential sensitivity of delay enables efficient encoding
Ideal for edge and always‑on AI applications

Hyperlocalized Computation

In time‑domain CiM:

Each memory cell generates a local pulse
Pulses interact only with nearest neighbors
No large shared analog nodes or global summation lines

This hyperlocalized signaling significantly improves robustness to interconnect parasitics and noise.

Digital‑Friendly Routing and Buffering

Signals are propagated using:

Inverters and digital buffers
Standard cell logic

This eliminates the need for:

Linear amplifiers
Precision biasing
Power‑hungry analog buffers

Digitization via Time‑to‑Digital Conversion (TDC)

Why TDC Instead of ADC

Time‑domain CiM naturally pairs with time‑to‑digital converters (TDCs) rather than ADCs.

Key advantages of TDCs:

Implemented using digital gates
Scales with Moore’s Law
Narrow pitch enables dense, parallel instantiation

Parallelism and Scalability

Unlike high‑resolution ADCs, which are area‑ and power‑intensive:

TDCs can be instantiated per column or per tile
Enable true parallel readout of CiM arrays

Self‑Tracking and Variation Tolerance

Time‑domain systems can be designed to:

Track delay variations inherently
Use reference paths for continuous calibration
Eliminate costly one‑time or periodic calibration loops

This self‑tracking behavior dramatically reduces design complexity and improves yield.

Implications for AI Accelerators

Time‑domain CiM is particularly well‑matched to AI workloads:

Multiply‑accumulate dominance
Tolerance to modest precision
Extreme sensitivity to energy per operation

By combining:

Reduced data movement
Ultra‑low‑power operation
Digital‑friendly scalability

Time‑domain CiM offers a compelling architecture for next‑generation AI accelerators across cloud, edge, and embedded domains.

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Conclusion

The recent emergence of heavily funded startups such as Unconventional AI, combined with growing skepticism around the scalability of conventional GPUs and amplitude‑based analog CiM, marks a pivotal moment for the AI hardware ecosystem. The industry is actively searching for computing substrates that can deliver orders‑of‑magnitude improvements in energy efficiency without sacrificing robustness or manufacturability.

The limitations of charge‑ and current‑domain CiM are not merely engineering challenges—they are fundamental constraints rooted in voltage scaling, parasitics, and analog sensitivity. Time‑domain computing represents a paradigm shift that leverages the strengths of advanced CMOS technologies rather than fighting their weaknesses.

By encoding computation in time, time‑domain CiM enables:

Robust accumulation without analog summation nodes
Wide dynamic range independent of supply voltage
Ultra‑low‑power, subthreshold operation
Digital‑friendly scalability through TDC‑based readout
Intrinsic tolerance to process and environmental variation

As the AI industry confronts its scaling and energy limits, time‑domain compute-in-memory offers a clear and technically grounded path forward.

The time for time‑domain computing is not in the future — it is now.

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Ankush Goel, VP of Silicon Engineering, ANAFLASH

Shahrzad Naraghi, Chief Technology Officer, ANAFLASH

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