Time-Domain CiM Featured in JSSC

A Two-Step Time-Domain Logic-Compatible Embedded-Flash Computing-in-Memory Macro for On-Device AI

Computing in memory (CIM) has emerged as a promising architecture that can significantly reduce power consumption and latency in edge artificial intelligence (AI) devices. For battery-constrained edge devices, non-volatile memories (NVMs) are ideal due to their ability to retain neural network parameters even when powered down, ensuring rapid response time upon device wake-up. However, the tradeoff between energy efficiency and computing precision in CIM implementation limits their ability to support various computational workloads in edge AI. In this article, we propose a logic-compatible embedded-flash macro with two-step time-domain computation. The proposed macro computes through dual capacitors operating in a ping-pong manner, enabling simultaneous activation of up to 128 cells with signed weights and achieving 10-bit output precision with the option of further scalable resolution. Apipelined time-to-digital conversion architecture further reduces conversion latency by performing computation in parallel, and an on-chip rectified linear unit (ReLU) suppresses unnecessary time-to-digital conversions for negative outputs, further improving energy efficiency. The proposed CIM prototype achieves a peak throughput of 639.38 GOPS and peak normalized energy efficiency of 1517.16 TOPS/W using 3-bit weights, 4-bit activations, and 10-bit outputs, with a measured matrix-vector multiplication (MVM) error deviation of less than 1%.

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Source:

https://ieeexplore.ieee.org/document/11663409